737 lines
18 KiB
C
737 lines
18 KiB
C
/* SPDX-License-Identifier: GPL-2.0 */
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/*
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* Copyright (c) 2023, Jaguar Micro. All rights reserved.
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*
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* This software is available to you under a choice of one of two
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* licenses. You may choose to be licensed under the terms of the GNU
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* General Public License (GPL) Version 2, available from the file
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* COPYING in the main directory of this source tree, or the
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* OpenIB.org BSD license below:
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*
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* Redistribution and use in source and binary forms, with or
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* without modification, are permitted provided that the following
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* conditions are met:
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*
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* - Redistributions of source code must retain the above
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* copyright notice, this list of conditions and the following
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* disclaimer.
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*
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* - Redistributions in binary form must reproduce the above
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* copyright notice, this list of conditions and the following
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* disclaimer in the documentation and/or other materials
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* provided with the distribution.
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*
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* THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
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* EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
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* MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
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* NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS
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* BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN
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* ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN
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* CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
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* SOFTWARE.
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*/
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#ifndef _CRETE_H_
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#define _CRETE_H_
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#include <linux/pci.h>
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#include <linux/timecounter.h>
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#include <linux/net_tstamp.h>
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#include <linux/ptp_clock_kernel.h>
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#include <linux/bitops.h>
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#include <linux/if_vlan.h>
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#include <linux/version.h>
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#include <net/dst_metadata.h>
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#ifndef USE_JM_AUX_BUS
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#include <linux/auxiliary_bus.h>
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#else
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#include "linux/auxiliary_bus.h"
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#endif
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#include "kcompat_std_defs.h"
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#include "rdma.h"
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#include "crete_txrx.h"
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#include "crete_sriov.h"
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#include "crete_eswitch.h"
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#include "crete_dcb_nl.h"
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#include "crete_lag.h"
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#include "crete_debugfs_statistics.h"
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/*micro filed*/
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#define MAX_MSIX_ENTRIES 10
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#define MAX_Q_VECTORS 8
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#define CRETE_MAX_TX_QUEUES 8
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#define CRETE_MAX_RX_QUEUES 8
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#define CRETE_DEFAULT_TXD 256
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#define CRETE_DEFAULT_TX_WORK 128
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#define CRETE_MIN_TXD 80
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#define CRETE_MAX_TXD 4096
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#define CRETE_DEFAULT_RXD 256
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#define CRETE_MIN_RXD 80
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#define CRETE_MAX_RXD 4096
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#define CRETE_DEFAULT_ITR 3 /* dynamic */
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#define CRETE_MAX_ITR_USECS 10000
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#define CRETE_MIN_ITR_USECS 10
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#define CRETE_Q_VECTORS 1
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#define CRETE_ETH_PKT_HDR_PAD (ETH_HLEN + ETH_FCS_LEN)
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/* As per the EAS the maximum supported size is 9.5KB (9728 bytes) */
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#define MAX_JUMBO_FRAME_SIZE 0x2600
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#define MAX_STD_JUMBO_FRAME_SIZE 9216
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/* Supported Rx Buffer Sizes */
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#define CRETE_RXBUFFER_256 256
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#define CRETE_RXBUFFER_1536 1536
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#define CRETE_RXBUFFER_2048 2048
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#define CRETE_TS_HDR_LEN 16
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#define ALIGN_TO_DW(a) (((a) + 3ULL) & (~3))
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#define CRETE_CMD_WQ_MAX_NAME 32
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/* device desc offset */
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#define CRETE_JDH_OFFSET (CRETE_LEGACY_RESV)
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#define CRETE_JND_OFFSET (CRETE_JDH_OFFSET + sizeof(struct crete_desc_hdr))
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#define CRETE_JRD_OFFSET (CRETE_JND_OFFSET + sizeof(struct crete_ndc_dpt))
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#define CRETE_CAP_OFFSET 8
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enum {
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CRETE_FLAG_DISABLE_ALL_ADEV = 1 << 0,
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CRETE_PAGE_MODE = 1 << 1,
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CRETE_FLAG_HAS_MSIX = 1 << 13,
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};
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#define CRETE_LEGACY_RESV 0x0
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#define CRETE_MAGIC_NUM 0xdeadbeef
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#define CRETE_EVENT_VECTOR 0
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#define CRETE_CMD_DATA_BLOCK_SIZE 512
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enum crete_coredev_type {
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CRETE_COREDEV_PF,
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CRETE_COREDEV_VF,
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CRETE_COREDEV_SF,
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};
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enum crete_device_type {
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CRETE_DEVICE_CRETE,
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CRETE_DEVICE_PNIC,
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CRETE_DEVICE_RNIC,
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CRETE_DEVICE_FAKE,
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};
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enum {
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CRETE_PCI_DEV_IS_VF = 1 << 0,
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};
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#define CRETE_ADEV_NAME "crete_core"
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/*enum filed*/
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enum crete_state_t {
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__CRETE_TESTING,
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__CRETE_RESETING,
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__CRETE_DOWN,
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};
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/* Device Capability type */
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enum crete_cap_type {
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CRETE_NET_CONF_CAP = 2,
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CRETE_RDMA_CONF_CAP = 3,
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CRETE_OFFLOAD_CONF_CAP = 4,
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CRETE_RES_CONF_CAP = 5,
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CRETE_DEVS_CONF_CAP = 6,
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CRETE_SHARES_DB_CAP = 7,
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CRETE_CAP_MAX,
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};
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struct crete_init_seg {
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uint16_t fw_ver_minor;
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uint16_t fw_ver_major;
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uint16_t fw_revision;
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uint16_t cmd_interface_rev;
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uint8_t cp_status;
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uint8_t cp_caps;
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uint8_t dev_status;
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uint8_t reset_dev;
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uint32_t cmd_path_db;
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uint32_t cmd_path_entry[16];
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uint32_t resv1[8];
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uint32_t event_buffer[8];
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uint32_t event_buffer_addr_low;
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uint32_t event_buffer_addr_hi;
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uint8_t event_busy;
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uint8_t event_buffer_size;
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uint16_t event_vector;
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uint32_t event_credit_doorbell;
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uint16_t resv2;
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uint16_t aq_queue_size;
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uint32_t aq_queue_db;
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uint32_t aq_base_addr_low;
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uint32_t aq_base_addr_hi;
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uint32_t shared_res_lock;
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uint32_t shared_res_db;
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uint32_t extra_admin_db;
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uint32_t resv3[13];
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uint32_t timestamp[2];
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} __packed;
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struct cmd_info {
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uint32_t owner:1;
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uint32_t out_inline:1;
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uint32_t in_inline:1;
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uint32_t event_notify:1;
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uint32_t status:4;
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uint32_t sig:8;
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uint32_t cmd_encap_type:8;
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uint32_t cid:8;
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};
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struct crete_cmd_entry {
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uint32_t in_len;
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uint32_t out_len;
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uint64_t in_ptr;
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uint64_t out_ptr;
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uint8_t inline_data[36];
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union {
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struct cmd_info cmd_info;
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uint32_t cmd_info_data;
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};
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} __packed;
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struct crete_cmd_prot_block {
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u8 sig;
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u8 block_num;
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u8 rsvd0;
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u8 cid;
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uint32_t cmd_data_len;//CRETE_CMD_DATA_BLOCK_SIZE
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uint64_t next;
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uint32_t next_len;
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uint32_t cmd_data[];
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} __packed;
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struct crete_cmd_mailbox {
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void *buf;
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dma_addr_t dma;
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struct crete_cmd_mailbox *next;
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};
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struct crete_cmd_msg {
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struct list_head list;
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u32 msg_mode;
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u32 len;
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struct crete_cmd_mailbox *next;
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u8 inline_data[36]; //inline bd Optimize todo
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}__aligned(8);
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#define CRETE_MAX_COMMANDS 32
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struct crete_cmd_work_ent {
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unsigned long state;
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struct crete_cmd_msg *inb;
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struct crete_cmd_msg *outb;
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void *out;
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int out_size;
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int idx;
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struct completion handling;
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struct completion done;
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struct crete_cmd *cmd;
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struct work_struct work;
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struct crete_cmd_entry *lay;
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int ret;
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u8 status;//fw return cmd status
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u16 cmd_id;
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bool polling;
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u64 ts1;
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u64 ts2;
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/* Track the max comp handlers */
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refcount_t refcnt;
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};
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struct crete_cmd {
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struct crete_nb nb;
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u8 mode;
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u8 poll_mode;
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void *cmd_buf;
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dma_addr_t cmd_dma;
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u32 cmd_size;
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u32 cmd_stride;
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struct dma_pool *pool;
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int max_cmds;
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unsigned long bitmask;
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char wq_name[CRETE_CMD_WQ_MAX_NAME];
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struct workqueue_struct *wq;
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struct semaphore sem;
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spinlock_t alloc_lock;
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struct crete_cmd_work_ent *ent_arr[CRETE_MAX_COMMANDS];
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};
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/* for test qp create */
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struct crete_qbase_info {
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void *va;
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dma_addr_t pa;
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};
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struct crete_queue_info {
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uint8_t rx_qid;
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uint16_t q_size;
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uint16_t vec[2];
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struct crete_qbase_info sq[2];
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struct crete_qbase_info cq[2];
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};
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/*
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*Device Capability Descriptor
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*Device Capability Descriptor Header
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*/
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struct crete_desc_hdr {
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uint32_t magic;
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uint32_t cap_cnt:8;
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uint32_t len:12;
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uint32_t offset:12;
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};
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// net device configuration descriptor,cap_type = 2
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struct crete_ndc_dpt {
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uint32_t type:8;
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uint32_t resv:24;
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uint32_t len:12;
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uint32_t offset:20;
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};
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// Rdma Device Configuration Descriptor,cap_type = 3
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struct crete_rdma_cfg_desc {
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uint32_t cap_type:8;
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uint32_t resv:24;
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uint32_t len:12;
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uint32_t offset:20;
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};
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// Offload Configuration Descriptor,cap_type = 4
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struct crete_offload_cfg_desc {
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uint32_t cap_type:8;
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uint32_t resv:24;
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uint32_t len:12;
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uint32_t offset:20;
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};
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// resource configuration descriptor,cap_type = 5
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struct crete_rc_dpt {
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uint32_t type:8;
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uint32_t ru_size:12;
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uint32_t ru_max:12;
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uint32_t len:12;
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uint32_t offset:20;
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};
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//Device-specific Configuration Descriptor,cap_type = 6
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struct crete_devs_dpt {
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uint32_t cap_type:8;
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uint32_t resv:24;
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uint32_t len:12;
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uint32_t offset:20;
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};
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//Shared Data Descriptor,cap_type = 7
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struct crete_shared_dpt {
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uint32_t cap_type:8;
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uint32_t len:24;
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uint32_t offset;
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};
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/* hw */
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struct crete_hw {
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struct crete_init_seg __iomem *io_addr;
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struct crete_desc_hdr jdh;
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struct crete_ndc_dpt jnd;
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struct crete_rdma_cfg_desc rdma_desc;
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struct crete_offload_cfg_desc offload_desc;
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struct crete_rc_dpt jrd;
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struct crete_devs_dpt dev_spec_desc;
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struct crete_shared_dpt share_data_desc;
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};
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struct crete_aux_dev {
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struct crete_core_dev *core_dev;
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struct auxiliary_device adev;
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int idx;
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};
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#define CRETE_MAX_UC_ADDRS 4
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#define CRETE_MAX_MC_ADDRS 16
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#define L2_SET_RX_MASK_REQ_MASK_MCAST 0x1UL
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#define L2_SET_RX_MASK_REQ_MASK_ALL_MCAST 0x2UL
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#define L2_SET_RX_MASK_REQ_MASK_BCAST 0x4UL
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#define L2_SET_RX_MASK_REQ_MASK_PROMISCUOUS 0x8UL
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struct crete_priv {
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struct crete_core_dev *coredev;
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struct crete_esw_rep *rep;
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struct net_device *netdev;
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struct workqueue_struct *wq;
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struct work_struct set_rx_mode_work;
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struct crete_dcbx dcbx;
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struct crete_dcbx_dp dcbx_dp;
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/* vport rx mode */
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u32 rx_mask;
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__le64 fw_l2_filter_id[CRETE_MAX_UC_ADDRS];
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/* index 0 always dev_addr */
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u16 uc_filter_count;
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u8 *uc_list;
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u8 *mc_list;
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int mc_list_size;
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int mc_list_count;
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int vlan_range_num;
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};
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struct crete_debugfs_entries {
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struct dentry *dbg_root;
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struct dentry *lag_debugfs;
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struct dentry *statistics_debugfs;
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};
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struct crete_irq_info {
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char name[IFNAMSIZ + 2];
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irq_handler_t handler;
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unsigned int vector;
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u8 requested:1;
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u8 have_cpumask:1;
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};
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struct crete_pf_info {
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u16 fw_fid;
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u16 port_id;
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u8 mac_addr[ETH_ALEN];
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u32 first_vf_id;
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u16 active_vfs;
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u16 registered_vfs;
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u16 max_vfs;
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void *hwrm_cmd_req_addr[4];
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dma_addr_t hwrm_cmd_req_dma_addr[4];
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struct crete_vf_info *vf;
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struct kobject *config;
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struct kobject *groups_config;
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struct crete_sriov_vf_sysfs *vf_sysfs;
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};
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struct rdma_dev_adapt {
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unsigned int flags;
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unsigned int priv_flags;
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unsigned int bar_offset;
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unsigned int bar_len;
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phys_addr_t uar_base;
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unsigned int uar_size;
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void __iomem *reg_addr; /*bar addr*/
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__le32 *cmd_db_reg; /* cmd db addr*/
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__le32 __iomem *eq_db_reg;
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struct mutex intf_state_mutex;
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unsigned int vector_base;
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unsigned int vector_num;
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};
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struct crete_qp_context {
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__le16 rx_qid; /* must be even */
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__le16 event_credit;
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__le16 rx_sq_vq_size; /* vnet rx vq size */
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__le16 rx_cq_size; /* unless for vnet */
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__le16 tx_sq_vq_size; /* tx vq size for vnet */
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__le16 tx_cq_size; /* useless for vnet */
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__le16 rx_queue_vec; /* rx queue interrupt vector */
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__le16 tx_queue_vec; /* tx queue interrupt vector */
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__le64 rx_sq_desc_base; /* rx queue desc base address for vnet */
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__le64 rx_cq_used_base; /* rx cq address ,rx used ring address for vnet */
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__le64 tx_sq_desc_base; /* tx sq address, tx queue desc address for vnet */
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__le64 tx_cq_used_base; /* tx cq address, tx queue used ring address for vnet */
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};
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struct crete_queue_context {
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__le16 qid; /* must be even */
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__le16 queue_size; /* vnet io vq size */
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__le16 cq_size; /* vnet cq size */
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__le16 queue_vec; /*queue interrupt vector */
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__le16 resv; /*reserved */
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__le64 queue_desc_base; /* rx queue desc base address for vnet */
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__le64 queue_used_base; /* rx cq address ,rx used ring address for vnet */
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};
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struct crete_core_qpcap {
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u16 max_queue_size;
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u8 max_qp_num;
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u8 ctrl_queue_size;
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};
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struct crete_core_cap {
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struct crete_core_qpcap qpcap;
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__le64 hw_features;
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__le64 driver_features;
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// pf core cap need more
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};
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struct crete_qp_cap {
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u8 ctrl_queue_size;
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u8 max_qp_num;
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__le16 max_queue_size;
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} __packed;
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struct crete_txq_stats {
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struct u64_stats_sync syncp;
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u64 packets;
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u64 bytes;
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u64 kicks;
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};
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struct crete_rxq_stats {
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struct u64_stats_sync syncp;
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u64 packets;
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u64 bytes;
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u64 drops;
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u64 kicks;
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};
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#define CRETE_TXQ_STATS(m) offsetof(struct crete_txq_stats, m)
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#define CRETE_RXQ_STATS(m) offsetof(struct crete_rxq_stats, m)
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struct crete_core_dev {
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#define CRETE_MAX_MSIX_NUM 4096U
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spinlock_t lock;
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struct device *device;
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void __iomem *db_base;
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struct pci_dev *pdev;
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struct crete_core_cap cap;
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struct crete_txring_info *txring;
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u16 *txring_mapping;
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// u16 txring_size;
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struct crete_rxring_info *rxring;
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u16 *rxring_mapping;
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// u16 rxring_size;
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u16 ring_size;
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// ring parameters
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u32 rx_buf_size;
|
|
u32 rx_buf_use_size; /* useable size */
|
|
u16 rx_offset;
|
|
u16 rx_dma_offset;
|
|
|
|
struct crete_db *db;
|
|
//struct crete_core_cap *cap;
|
|
struct crete_napi *jnapi;
|
|
struct crete_rxcp_ring_info *rxcpring;
|
|
struct crete_txcp_ring_info *txcpring;
|
|
|
|
u16 max_qp_num;
|
|
unsigned long state;
|
|
|
|
struct net_device *netdev;
|
|
u64 netdev_features;
|
|
u64 offload_features;
|
|
unsigned int flags;
|
|
u32 rss_queues;
|
|
u8 __iomem *io_addr;
|
|
phys_addr_t bar_addr; //for further consider
|
|
|
|
struct crete_hw hw;
|
|
struct crete_queue_info q_info; // for create qp test
|
|
struct crete_aux_dev **adev;
|
|
int adev_idx;
|
|
struct crete_irq_info *irq_info;
|
|
struct crete_cmd cmd;
|
|
struct crete_event_irq *event_irq;
|
|
u16 irq_num;
|
|
unsigned long irqbit[BITS_TO_LONGS(CRETE_MAX_MSIX_NUM)];
|
|
struct msix_entry *msix_ent;
|
|
enum crete_coredev_type coredev_type;
|
|
enum crete_device_type device_type;
|
|
struct crete_pf_info pf;
|
|
struct crete_vf_info vf;
|
|
bool sriov_cfg;
|
|
|
|
struct jm_rdma_core rdma_coredev;
|
|
struct rdma_dev_adapt rdma_adp;
|
|
|
|
struct crete_eswitch *eswitch;
|
|
struct crete_lag_cap lag_cap;
|
|
struct crete_debugfs_entries dbg;
|
|
struct crete_lag *lag_dev;
|
|
struct crete_debugfs_statistics *debugfs_statis;
|
|
u16 sfi_id;
|
|
u16 lag_enable;
|
|
};
|
|
|
|
|
|
|
|
enum crete_feature_type {
|
|
CRETE_FEATURE_NETDEV,
|
|
CRETE_FEATURE_OFFLOAD
|
|
};
|
|
|
|
static inline unsigned int crete_rd32(struct crete_core_dev *p, u32 reg)
|
|
{
|
|
u8 __iomem *ioaddr = READ_ONCE(p->io_addr);
|
|
u32 value = 0;
|
|
|
|
value = readl(&ioaddr[reg]);
|
|
|
|
return value;
|
|
}
|
|
|
|
static inline void crete_ioread32(void __iomem *addr, void *buffer,
|
|
unsigned int count)
|
|
{
|
|
int i = 0;
|
|
u32 *buf = buffer;
|
|
u8 __iomem *address = addr;
|
|
|
|
if (count) {
|
|
for (i = 0; i < count; i++)
|
|
readsl(address + i * 4, buf++, 1);
|
|
}
|
|
}
|
|
|
|
static inline void crete_iowrite32(void __iomem *addr, void *buffer,
|
|
unsigned int count)
|
|
{
|
|
int i = 0;
|
|
u32 *buf = buffer;
|
|
u8 __iomem *address = addr;
|
|
|
|
if (count) {
|
|
for (i = 0; i < count; i++)
|
|
writesl(address + i * 4, buf++, 1);
|
|
}
|
|
}
|
|
|
|
static inline struct device *crete_hw_to_dev(struct crete_hw *hw)
|
|
{
|
|
struct crete_core_dev *core_dev = container_of(hw, struct crete_core_dev, hw);
|
|
|
|
return &core_dev->pdev->dev;
|
|
}
|
|
int crete_adev_idx_alloc(void);
|
|
void crete_adev_idx_free(int idx);
|
|
static inline bool crete_sriov_is_enabled(struct crete_core_dev *dev)
|
|
{
|
|
return pci_num_vf(dev->pdev) ? true : false;
|
|
}
|
|
|
|
static inline bool crete_core_is_pf(const struct crete_core_dev *dev)
|
|
{
|
|
return dev->coredev_type == CRETE_COREDEV_PF;
|
|
}
|
|
|
|
static inline bool crete_core_is_vf(const struct crete_core_dev *dev)
|
|
{
|
|
return dev->coredev_type == CRETE_COREDEV_VF;
|
|
}
|
|
|
|
static inline bool crete_have_rdma_cap(const struct crete_core_dev *dev)
|
|
{
|
|
return dev->hw.rdma_desc.cap_type == CRETE_RDMA_CONF_CAP;
|
|
}
|
|
|
|
static inline bool crete_have_net_cap(const struct crete_core_dev *dev)
|
|
{
|
|
return dev->hw.jnd.type == CRETE_NET_CONF_CAP;
|
|
}
|
|
|
|
static inline u16 fw_ver_maj(struct crete_core_dev *dev)
|
|
{
|
|
struct crete_hw *hw = &dev->hw;
|
|
|
|
return readw(&hw->io_addr->fw_ver_major);
|
|
}
|
|
|
|
static inline u16 fw_ver_min(struct crete_core_dev *dev)
|
|
{
|
|
struct crete_hw *hw = &dev->hw;
|
|
|
|
return readw(&hw->io_addr->fw_ver_minor);
|
|
}
|
|
|
|
static inline u16 fw_ver_sub(struct crete_core_dev *dev)
|
|
{
|
|
struct crete_hw *hw = &dev->hw;
|
|
|
|
return readw(&hw->io_addr->cmd_interface_rev);
|
|
}
|
|
|
|
static inline u16 fw_ver_rev(struct crete_core_dev *dev)
|
|
{
|
|
struct crete_hw *hw = &dev->hw;
|
|
|
|
return readw(&hw->io_addr->fw_revision);
|
|
}
|
|
|
|
int crete_req_msixirq(struct crete_core_dev *core_dev);
|
|
void crete_free_msixirq(struct crete_core_dev *core_dev, int irq);
|
|
|
|
static inline bool __crete_test_bit(const u64 features, unsigned int fbit)
|
|
{
|
|
/* Did you forget to fix assumptions on max features? */
|
|
if (__builtin_constant_p(fbit))
|
|
BUILD_BUG_ON(fbit >= 64);
|
|
else
|
|
WARN_ON_ONCE(fbit >= 64);
|
|
|
|
return features & BIT_ULL(fbit);
|
|
}
|
|
|
|
static inline bool crete_has_feature(const struct crete_core_dev *cdev,
|
|
enum crete_feature_type feature_type, unsigned int fbit)
|
|
{
|
|
if (feature_type == CRETE_FEATURE_NETDEV)
|
|
return __crete_test_bit(cdev->netdev_features, fbit);
|
|
else
|
|
return __crete_test_bit(cdev->offload_features, fbit);
|
|
}
|
|
|
|
/* NEED_ETH_HW_ADDR_SET
|
|
*
|
|
* eth_hw_addr_set was added by upstream commit
|
|
* 48eab831ae8b ("net: create netdev->dev_addr assignment helpers")
|
|
*
|
|
* Using eth_hw_addr_set became required in 5.17, when the dev_addr field in
|
|
* the netdev struct was constified. See 48eab831ae8b ("net: create
|
|
* netdev->dev_addr assignment helpers")
|
|
*/
|
|
#ifdef NEED_ETH_HW_ADDR_SET
|
|
static inline void eth_hw_addr_set(struct net_device *dev, const u8 *addr)
|
|
{
|
|
ether_addr_copy(dev->dev_addr, addr);
|
|
}
|
|
#endif /* NEED_ETH_HW_ADDR_SET */
|
|
|
|
int crete_cmd_init(struct crete_core_dev *cdev);
|
|
int crete_event_init(struct crete_hw *hw);
|
|
void crete_cmd_exit(struct crete_core_dev *cdev);
|
|
void crete_event_exit(struct crete_hw *hw);
|
|
int crete_adev_init(struct crete_core_dev *core_dev);
|
|
void crete_adev_cleanup(struct crete_core_dev *core_dev);
|
|
int crete_rescan_drivers_locked(struct crete_core_dev *core_dev);
|
|
int crete_rescan_drivers(struct crete_core_dev *dev);
|
|
void crete_dev_list_lock(void);
|
|
void crete_dev_list_unlock(void);
|
|
int crete_dev_list_trylock(void);
|
|
void crete_sriov_disable(struct pci_dev *pdev);
|
|
int crete_register_device(struct crete_core_dev *core_dev);
|
|
void crete_unregister_device(struct crete_core_dev *core_dev);
|
|
|
|
void crete_detach_device(struct crete_core_dev *core_dev);
|
|
int crete_attach_device(struct crete_core_dev *core_dev);
|
|
int crete_change_mac_addr(struct net_device *netdev, void *p);
|
|
void crete_set_rx_mode(struct net_device *dev);
|
|
void crete_init_msix(struct crete_core_dev *core_dev);
|
|
void crete_exit_irq(struct crete_core_dev *core_dev);
|
|
extern struct dentry *crete_debugfs_root;
|
|
void crete_register_debugfs(void);
|
|
void crete_unregister_debugfs(void);
|
|
struct dentry *crete_debugfs_get_dev_root(struct crete_core_dev *dev);
|
|
extern const struct net_device_ops crete_netdev_ops;
|
|
extern const struct ethtool_ops crete_ethtool_ops;
|
|
#endif
|