/* SPDX-License-Identifier: GPL-2.0-only */
/*
 * JaguarMicro virt device driver for virtio dataplane offloading
 *
 * Copyright (C) 2020 JaguarMicro Corporation.
 *
 * Author: Angus Chen <angus.chen@jaguarmicro.com>
 *
 */

#ifndef _CRETE_VDPA_DEV_H_
#define _CRETE_VDPA_DEV_H_

#include <linux/pci.h>
#include <linux/pci_regs.h>
#include <linux/vdpa.h>
#include <uapi/linux/virtio_net.h>
#include <uapi/linux/virtio_blk.h>
#include <uapi/linux/virtio_config.h>
#include <uapi/linux/virtio_pci.h>
#include <linux/auxiliary_bus.h>
#include "../crete-core/crete_cmd.h"
#include "kcompat_generated_defs.h"
/* Max 8 data queue pairs(16 queues) and one control vq for now. */
#define CORSICA_MAX_QUEUES          65
#define CORSICA_MAX_QUEUES_NOCTRL   64

#define CORSICA_QUEUE_ALIGNMENT	PAGE_SIZE
/*attention pls ,it's the depth of queue*/
#define CORSICA_QUEUE_SIZE_MAX  1024
#define CORSICA_QUEUE_SIZE_MIN	64
#define CORSICA_MSI_CONFIG_OFF	0
#define CORSICA_MSI_QUEUE_OFF	1
#define CORSICA_PCI_MAX_RESOURCE	6
#define VHOST_F_LOG_ALL 26
#define VHOST_ACCESS_WO      0x2
#define DEBUG



#define CORSICA_ERR(pdev, fmt, ...)	dev_err(&pdev->dev, fmt, ##__VA_ARGS__)
#define CORSICA_DBG(pdev, fmt, ...)	dev_dbg(&pdev->dev, fmt, ##__VA_ARGS__)
#define CORSICA_INFO(pdev, fmt, ...)	dev_info(&pdev->dev, fmt, ##__VA_ARGS__)

#define CORSICA_DEV_CONFIG_OFFSIZE 0x40
#define CORSICA_LOG_BASE_L 0x2
#define CORSICA_LOG_BASE_H 0x6
#define CORSICA_32_BIT_MASK       0xffffffff
#define CORSICA_LOG_BASE          0x100000000000
#define CORSICA_LM_DISABLE        0x0
#define CORSICA_LM_ENABLE         0x1
#define CORSICA_LM_STOP_DEV       0x2
#define CORSICA_LM_ENABLE_VF      0x4
#define CORSICA_LM_ENABLE_PF      0x8
#define CORSICA_DEV_STOPED       0x4

#define  VIRTIO_NET_CONFIG_OFFSET_MAC offsetof(struct virtio_net_config, mac)
#define  VIRTIO_NET_CONFIG_OFFSET_MTU offsetof(struct virtio_net_config, mtu)
#define  VIRTIO_NET_CONFIG_OFFSET_STATUS offsetof(struct virtio_net_config, status)
#define CONFIG_ENABLE_TLP 0

#define CRETE_LOG_BASE_IOVA     0x100000000000
/*************************support bclinux********************************/

#ifndef HAVE_VDPA_MGMTDEV_OPS
struct vdpa_dev_set_config {
	struct {
		u8 mac[ETH_ALEN];
		u16 mtu;
		u16 max_vq_pairs;
	} net;
	u64 mask;
};

struct vdpa_mgmtdev_ops;

struct vdpa_mgmt_dev {
	struct device *device;
	const struct vdpa_mgmtdev_ops *ops;
	struct virtio_device_id *id_table;
	u64 config_attr_mask;
	struct list_head list;
	u64 supported_features;
	u32 max_supported_vqs;
};


struct vdpa_mgmtdev_ops {
	int (*dev_add)(struct vdpa_mgmt_dev *mdev, const char *name,
		       const struct vdpa_dev_set_config *config);
	void (*dev_del)(struct vdpa_mgmt_dev *mdev, struct vdpa_device *dev);
};

#endif


enum crete_net_status {
	CRETE_NET_DEV_STARTUP,
	CRETE_NET_DEV_FEATURE_OK,
	CRETE_NET_DEV_DEV_OK,
	CRETE_NET_DEV_STOPPED
};

#define CRETE_RX_SEQ 0
#define CRETE_TX_SEQ 1

struct crete_mig_log {
	u32 log_base_l;
	u32 log_base_h;
	/* TODO: need use array to store multiple iova */
	u32 iova_addr_l;
	u32 iova_addr_h;
	u32 iova_size_l;
	u32 iova_size_h;
	struct list_head list;
	unsigned int limit;
	unsigned int nmaps;
} __packed;

struct virtio_vdpa_config {
	union {
		struct virtio_net_config v_net_config;
		struct virtio_blk_config v_blk_config;
		u8     config_offset[CORSICA_DEV_CONFIG_OFFSIZE];
	};
};

struct crete_vdpa_config {
	struct virtio_vdpa_config vdpa_config;
	u16 lm_ctrl;
	u16 reserved;
	u32 log_base_l;
	u32 log_base_h;
	struct crete_mig_log mig_log;	
	u8 log_mask;
	u8 reserved1;
} __packed;

struct crete_vring_lm_cfg {
	u16 last_avail_idx;
	u16 can_used; /* indircat the `last_avail_idx already been getted */
};

struct crete_lm_cfg {
	struct crete_vdpa_config vdpa_lm_cfg;
	struct crete_vring_lm_cfg vring_lm_cfg[CORSICA_MAX_QUEUES];
};

#define crete_private_to_vd(adapter) \
	(&((struct crete_adapter *)adapter)->vd)

struct vring_info {
	u64 desc;
	u64 avail;
	u64 used;
	u16 size;
	u16 last_avail_idx;
	bool ready;
	void __iomem *notify_addr;
	phys_addr_t notify_pa;
	u32 irq;
	u32 irqvec;
	struct vdpa_callback cb;
	char msix_name[256];
};

struct crete_iotlb_map {
	struct list_head link;
	u64 start;
	u64 last;
	u64 size;
	u64 addr;
	u32 perm;
	u32 flags_padding;
	u64 __subtree_last;
	void *opaque;
};

struct crete_vdpa {
	struct crete_vnet_hw_cap *hcap; //vdpa device hw capability
/*********vdpa* soft capability*******/
	u8 status;
	u32 generation;
	u16 qp_nums;
	u16 num_queues;
	u16 queue_size;
	u64 driver_features;
	u32 dev_type;
/************vdap queue***************************/
	struct vring_info vring[CORSICA_MAX_QUEUES];
	char config_msix_name[256];
	struct vdpa_callback config_cb;
	unsigned int config_irq;
	u32 config_size;
	u16 lm_ctrl;
	u16 announce_count;
	struct crete_mig_log mig_log;	
	bool have_hw_ctrl;
	bool have_soft_ctrl;
	bool have_ctrl_irq;
	bool host_polling;
	__le16 ctl_qlen;
	u8 __iomem *lm_cfg;
	struct crete_vring_lm_cfg vring_lm_cfg[CORSICA_MAX_QUEUES];
	struct crete_nb cnb;
	spinlock_t iommu_lock;
	struct iommu_domain *domain;
	struct vhost_iotlb resv_iotlb;
	struct mm_struct *mm;
};


struct crete_adapter {
	struct vdpa_device vdpa;
	struct virtio_net_config config;
	struct crete_core_dev *cdev;
	struct crete_vdpa vd;
	struct crete_vdpa_mgmtdev *priv;
};

struct crete_vnet_hw_cap {
	__le64 hw_features;
	__le16 max_vqpnum;
	__le16 io_qlen;
	__le16 ctl_qlen;
	bool  have_ctl;
	__le16 vdpa_max_vqs;
};

struct crete_vdpa_mgmtdev {
	struct vdpa_mgmt_dev mdev;
	struct crete_adapter  *adapter;
	struct crete_core_dev *cdev;
	struct crete_vnet_hw_cap hcap;
};

int crete_vdpa_set_hwstatus(struct crete_core_dev *core_dev, u8 status,
							struct device *dev);
int crete_vdpa_get_mgmt_info(struct crete_vdpa_mgmtdev *cvm);

int crete_vdpa_dev_add(struct vdpa_mgmt_dev *mdev, const char *name,
			      const struct vdpa_dev_set_config *config);

void crete_vdpa_dev_del(struct vdpa_mgmt_dev *mdev, struct vdpa_device *dev);
int crete_vdpa_set_device_type(struct crete_core_dev *core_dev);
#endif /* _CRETE_VDPA_DEV_H_ */